Fast AVS Prediction Residual and Integer DCT Implementations for VLIW DSP

The very-long-instruction-word architecture is widely used for DSP. In AVS coding process, the prediction residual and integer DCT are frequently called and the methods of optimizing the loops are significant for reducing coding time. Based on the VLIW character, the paper analyzes the optimization methods to accelerate the speed of prediction residual and integer DCT. The AVS prediction residual and integer DCT modules are optimized and simulated on the platform of TMS320DM6446. The experiments show that the instruction cycles are reduced by about 71% and 60% for prediction residual and 8 × 8 integer DCT separately.