DocumentCode
2875835
Title
A single chip NMOS ethernet controller
Author
Bell, Andrew ; Borriello, Gaetano
Author_Institution
Xerox Research Center, Palo Alto, CA, USA
Volume
XXVI
fYear
1983
fDate
23-25 Feb. 1983
Firstpage
70
Lastpage
71
Abstract
The design of an integrated NMOS controller for a 10Mb Ethernet will be described. In addition to handling protocol, redundancy checking and preamble, the chip includes a self-calibrating tapped delay line for clock and data extraction.
Keywords
Clocks; Cyclic redundancy check; Delay lines; Ethernet networks; Frequency; Logic; MOS devices; Physical layer; Transmitters; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1983.1156428
Filename
1156428
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