Title :
A single chip NMOS ethernet controller
Author :
Bell, Andrew ; Borriello, Gaetano
Author_Institution :
Xerox Research Center, Palo Alto, CA, USA
Abstract :
The design of an integrated NMOS controller for a 10Mb Ethernet will be described. In addition to handling protocol, redundancy checking and preamble, the chip includes a self-calibrating tapped delay line for clock and data extraction.
Keywords :
Clocks; Cyclic redundancy check; Delay lines; Ethernet networks; Frequency; Logic; MOS devices; Physical layer; Transmitters; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1983.1156428
