Title :
A sub 100ns static 64k CMOS EPROM with on-chip test functions
Author :
Knecht, M. ; Keshtbod, P. ; Simmons, G. ; Manley, M.
Author_Institution :
Signetics Corp., Sunnyvale, CA, USA
Abstract :
This report will cover the design of a sub 100ns 64K N-well CMOS EPROM with 1μW quiescent power dissipation. On-chip test circuits have been used to reduce the time required for testing and reliability screening. Typical access time is 80ns.
Keywords :
CMOS technology; Circuit testing; Clocks; Costs; Decoding; EPROM; MOS devices; Pulse amplifiers; Pulse circuits; Pulse generation;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1983.1156430
