Title :
Inverter chain test structure for yield improvement and projection
Author_Institution :
IBM Laboratories, Boeblingen, Germany
Abstract :
The detection and localization of defects in a VLSI RAM array has been accomplished by rewiring the cells into an inverter chain and testing for correct signal propagation. The defective device can then be subjected to microscopic measurements and electrical tests to determine the cause of failure, which is then communicated to the process engineer. The method is exemplified on a 20Kb MTL bipolar memory array, but can be applied to other circuits and technologies.
Keywords :
Automatic testing; Chip scale packaging; Circuit testing; Design engineering; Flip-flops; Impedance; Inverters; Laboratories; Monitoring; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1983.1156444
