DocumentCode
2876090
Title
Inverter chain test structure for yield improvement and projection
Author
Berger, H.
Author_Institution
IBM Laboratories, Boeblingen, Germany
Volume
XXVI
fYear
1983
fDate
23-25 Feb. 1983
Firstpage
84
Lastpage
85
Abstract
The detection and localization of defects in a VLSI RAM array has been accomplished by rewiring the cells into an inverter chain and testing for correct signal propagation. The defective device can then be subjected to microscopic measurements and electrical tests to determine the cause of failure, which is then communicated to the process engineer. The method is exemplified on a 20Kb MTL bipolar memory array, but can be applied to other circuits and technologies.
Keywords
Automatic testing; Chip scale packaging; Circuit testing; Design engineering; Flip-flops; Impedance; Inverters; Laboratories; Monitoring; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1983.1156444
Filename
1156444
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