DocumentCode :
2876091
Title :
FPGA-based Accelerator Design for RankBoost in Web Search Engines
Author :
Xu, Ning-Yi ; Cai, Xiong-Fei ; Gao, Rui ; Zhang, Lei ; Hsu, Feng-Hsiung
Author_Institution :
Microsoft Res. Asia, Beijing
fYear :
2007
fDate :
12-14 Dec. 2007
Firstpage :
33
Lastpage :
40
Abstract :
Search relevance is a key measurement for the usefulness of search engines. Shift of search relevance among search engines can easily change a search company´s market cap by tens of billions of dollars. With the ever-increasing scale of the Web, machine learning technologies have become important tools to improve search relevance ranking. RankBoost is a promising algorithm in this area, but it is not widely used due to its long training time. To reduce the computation time for RankBoost, we designed a FPGA-based accelerator system. The accelerator, plugged into a commodity PC, increased the training speed on MSN search engine data by 2 orders of magnitude compared to the original software implementation on a server. The proposed accelerator has been successfully used by researchers in the search relevance ranking .
Keywords :
Internet; field programmable gate arrays; learning (artificial intelligence); search engines; FPGA; RankBoost; Web search engines; accelerator design; machine learning; Application software; Bandwidth; Business; Computational efficiency; Computer aided instruction; Field programmable gate arrays; Large-scale systems; Machine learning algorithms; Search engines; Web search;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field-Programmable Technology, 2007. ICFPT 2007. International Conference on
Conference_Location :
Kitakyushu
Print_ISBN :
978-1-4244-1472-7
Electronic_ISBN :
978-1-4244-1472-7
Type :
conf
DOI :
10.1109/FPT.2007.4439229
Filename :
4439229
Link To Document :
بازگشت