Title :
Modeling redundancy in 64K to 16Mb DRAMs
Author_Institution :
IBM Geneneral Technology Division, Essex Junction, VT, USA
Abstract :
This paper will discuss a statistical model based on the level of individual and clustered defects, which has been applied to 64K, 256K, 1M, 4M and 16Mb DRAMs. The study predicts the optimum time for the introduction of the 64K to 16Mb RAM.
Keywords :
Circuit faults; Integrated circuit manufacture; Integrated circuit yield; Manufacturing; Productivity; Read only memory; Redundancy; Semiconductor device modeling; Statistics; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1983.1156446
