DocumentCode
2876133
Title
Efficient Physical Design Methodology for Reducing Test Power Dissipation of Scan-Based Designs
Author
Xu, Jun ; Li, Xiangku
Author_Institution
Key Lab. of Comput. Syst. & Archit., Chinese Acad. of Sci., Beijing, China
fYear
2009
fDate
9-11 July 2009
Firstpage
365
Lastpage
370
Abstract
Scan-based test methodology is used to resolve the sequential-test problem but suffers from high power dissipation. In this paper, we propose a scheme to prevent transitions of scan chain from reflecting into the circuit line. It not only can save 23% power consumption without performance loss, but also can be easily implemented with popular industrial design tools.
Keywords
boundary scan testing; integrated circuit design; integrated circuit testing; logic design; sequential circuits; shift registers; circuit line; physical design; power consumption; scan chain; scan-based design; scan-based test methodology; sequential circuit; sequential-test; shift mode; test power dissipation; Automatic test pattern generation; Circuit testing; Computer architecture; Controllability; Design methodology; Logic; Power dissipation; Registers; Sequential analysis; System testing; Capture mod; Critical path; Scan Design; Shift mode; Test power;
fLanguage
English
Publisher
ieee
Conference_Titel
Networking, Architecture, and Storage, 2009. NAS 2009. IEEE International Conference on
Conference_Location
Hunan
Print_ISBN
978-0-7695-3741-2
Type
conf
DOI
10.1109/NAS.2009.65
Filename
5197352
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