High Performance Hardware Implementation of SpikeProp Learning: Potential and Tradeoffs

In this paper the design of a dedicated high-performance hardware architecture for the SpikeProp algorithm is described. The proposed architecture performs the two main phases in spiking neural networks (SNNs) processing: recall and learning. The proposed architecture is flexible with respect to the number of neurons, the data precision to be used and the number of processing elements. Tradeoffs and limitations of a hardware-based learning rule for SNNs are analyzed. Performance statistics, error analysis and hardware resource consumption are provided. The proposed architecture obtains at least a 10X accelerator factor, and similar precision with respect to C-based SW implementation is obtained.