DocumentCode
2876368
Title
Thermal issues in stacked die packages
Author
Rencz, Marta
Author_Institution
MicReD Ltd, Budapest, Hungary
fYear
2005
fDate
15-17 March 2005
Firstpage
307
Lastpage
312
Abstract
After an introductory discussion of the thermal issues in stacked die packages in general, two major subjects are discussed in the paper: the qualification of die attach in stacked die structures and the questions of compact thermal modeling. An overview is given about the currently used techniques for the qualification of the die attach for failure analysis in stacked structures. The third part of the paper presents the state-of-the-art and the major issues of compact thermal modeling of stacked die packages.
Keywords
failure analysis; integrated circuit modelling; integrated circuit packaging; microassembling; thermal management (packaging); transients; compact thermal modeling; die attach qualification; stacked die packages; stacked structure failure analysis; thermal management; thermal transient measurements; wire bonding; Conducting materials; Conductive films; Electronic packaging thermal management; Electronics packaging; Integrated circuit packaging; Microassembly; Qualifications; Silicon; Thermal management; Thermal resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Thermal Measurement and Management Symposium, 2005 IEEE Twenty First Annual IEEE
ISSN
1065-2221
Print_ISBN
0-7803-8985-9
Type
conf
DOI
10.1109/STHERM.2005.1412197
Filename
1412197
Link To Document