Efficient and High-Throughput Implementations of AES-GCM on FPGAs

This paper addresses efficient and high-throughput implementations of AES-GCM optimized for FPGAs. Two main components, the AES engine and the modular multiplication over GF(2^m), are discussed and their complexities on FPGAs are shown. Instead of discussing the complexities by using AND and XOR gates as primitives, we present the complexity analysis directly based on FPGA primitives, e.g., Look-Up-Tables (LUTs). For the modular multiplier, the straightforward multiplication is used to get a speed-efficient design while the Karatsuba ´s algorithm is used to get an area-efficient design. For the AES engine, the composite field approach is adopted and then inner-round pipelining technology is applied. The estimated resource consumption returned by the complexity analysis provides a good criterion to minimize the influence of technology mapping. By optimizing and balancing the critical delay of sub-components, two high performance GCM implementations are presented on Xilinx Virtex-4 devices.