Title :
An 18V double level poly CMOS technology for nonvolatile memory and linear applications
Author :
Haken, R. ; Groves, I. ; Chung Wang ; Feger, W. ; Scott, D. ; Yee See ; Davies, R.
Author_Institution :
Texas Instruments Semiconductor Process-Design Center, Dallas, TX, USA
Abstract :
The process flow for a 4μ, 9-mask CMOS technology will be described. The procedure employs 0.8pF/mil2multidielectric poly to poly capacitors, silicided second poly and N-channel lightly doped drain extensions.
Keywords :
CMOS process; CMOS technology; Capacitors; Dielectrics; Immune system; Implants; Nonvolatile memory; Random access memory; Read-write memory; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1983.1156470
