Title :
A fault tolerant MOS-LSI for train controller applications
Author :
Masuda, I. ; Ueno, Masahiro ; Tashiro, Keiji ; Yasunami, M.
Author_Institution :
Hitachi Research Laboratory, Ibaraki, Japan
Abstract :
Fault-tolerant design techniques, which have resulted in the development of a fail-safe LSI circuit for train control applications, will be discussed. The design is based on bit-serial, time-sharing and frequency domain operation, as well as a layout method to restrict possible MOS failure modes.
Keywords :
Automatic control; Circuits; Fault tolerance; Fault tolerant systems; Large scale integration; Logic devices; Read only memory; Traffic control; Voltage; Wire;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1983.1156477
