Title :
NICFlex: A Functional Verification Accelerator for An RTL NIC Design
Author :
Jiang, Xianyang ; Li, Xiaomin ; Tian, Yue ; Wang, Kai
Author_Institution :
Chinese Acad. of Sci., Wuhan
Abstract :
A short time-to-market is very important for a chip, and verification takes the most (about 70%) of its design time. Network interface controller (NIC) is a key component for a supercomputer and other computing systems. To reduce verification time for such a market-demanding product plays a great role in relevant system design. In this paper, a functional verification accelerator NICFlex is presented for a register transfer level (RTL) NIC design. NICFlex accelerates verification process by both a software part and a hardware part. The software part runs as a simulation thread, and the hardware part is mapped into field programmable gate array (FPGA) logic together with a NIC wrapper. Compared to a conventional simulation verification method using ModelSim, NICFlex can accelerate the functional verification of an RTL NIC design for hundreds of times or more. With extension, NICFlex is promising for any functional verification acceleration of a generic RTL design.
Keywords :
field programmable gate arrays; logic design; mainframes; network interfaces; parallel machines; FPGA; ModelSim; NIC wrapper; NICFlex; RTL NIC design; computing systems; field programmable gate array; network interface controller; register transfer level; short time-to-market; supercomputer; verification accelerator; Acceleration; Computer interfaces; Computer networks; Control systems; Field programmable gate arrays; Hardware; Network interfaces; Programmable logic arrays; Supercomputers; Time to market;
Conference_Titel :
Field-Programmable Technology, 2007. ICFPT 2007. International Conference on
Conference_Location :
Kitakyushu
Print_ISBN :
978-1-4244-1472-7
Electronic_ISBN :
978-1-4244-1472-7
DOI :
10.1109/FPT.2007.4439266
