Title :
A 5000-gate bipolar masterslice LSI with 500ps loaded gate delay
Author :
Suzuki, M. ; Horiguchi, Shogo ; Sudo, Toshio
Author_Institution :
Nippon Tel.-Tel. Musashino Electrical Communication Laboratory, Tokyo, Japan
Abstract :
A fully ECL compatible bipolar master slice LSI with a loaded gate delay of 500ps and power dissipation of less than 6W will be reported. A 1.5μm design rule bipolar process employing three levels of metalization has been utilized.
Keywords :
Aluminum; Circuits; Delay; Large scale integration; Logic; Power dissipation; Power supplies; Regulators; Voltage; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1983.1156484
