Degradation of static behaviour of poly-Si CMOS inverters under high frequency operation

Author

Chen, Wei ; Wang, Mingxiang ; Zhou, Yan ; Wong, Man

Author_Institution

Dept. of Microelectron., Soochow Univ., Suzhou, China

fYear

2011

fDate

4-7 July 2011

Firstpage

1

Lastpage

3

Abstract

We studied the degradation of poly-Si CMOS inverters under high frequency operation. Increased low noise margin and logic threshold voltage, decreased high noise margin and gain were observed. Based on a previous drain current model of thin-film transistors (TFTs), voltage transfer characteristic of inverter is well described. Large degradation was observed in p-TFT instead of n-TFT after 10 ks operation. Dynamic negative bias temperature instability is considered to be the degradation mechanism leading to the inverter´s degradation.

Keywords

CMOS integrated circuits; invertors; CMOS inverters; drain current model; dynamic negative bias temperature instability; high frequency operation; inverter degradation mechanism; logic threshold voltage; static behaviour; thin film transistors; voltage transfer characteristic; Degradation; Fitting; Inverters; Stress; Thin film transistors; Threshold voltage; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2011 18th IEEE International Symposium on the

Conference_Location

Incheon

ISSN

1946-1542

Print_ISBN

978-1-4577-0159-7

Electronic_ISBN

1946-1542

Type

conf

DOI

10.1109/IPFA.2011.5992722

Filename

5992722