Title :
Multiply Accumulate Unit Optimised for Fast Dot-Product Evaluation
Author :
Kamp, William ; Bainbridge-Smith, Andrew
Author_Institution :
Univ. of Canterbury, Canterbury
Abstract :
A fast dot-product unit suitable for long word lengths is shown. Its implementation is based on computing only the significant partial products and exploiting the properties of the asymmetric signed digit redundant number representation. Optimal partial product packing and a carry propagation free adder combine to yield a MAC with high throughput. An example design of a low-pass FIR filter of 51 taps of 32 bit word-length was synthesised for the Altera cyclone II FPGA family. A filter clock speed of 220 MHz and a throughput of 12.9 MSamples/s was achieved.
Keywords :
FIR filters; adders; digital arithmetic; field programmable gate arrays; low-pass filters; Altera Cyclone II FPGA family; adder; asymmetric signed number; bit word-length; digit redundant number representation; fast dot-product evaluation; field programmable gate arrays; filter clock speed; frequency 220 MHz; low-pass FIR filter; multiply-and-accumulate unit; optimal partial product packing; Algorithm design and analysis; Array signal processing; Clocks; Cyclones; Field programmable gate arrays; Finite impulse response filter; Microprocessors; Signal design; Signal processing algorithms; Throughput;
Conference_Titel :
Field-Programmable Technology, 2007. ICFPT 2007. International Conference on
Conference_Location :
Kitakyushu
Print_ISBN :
978-1-4244-1472-7
Electronic_ISBN :
978-1-4244-1472-7
DOI :
10.1109/FPT.2007.4439283
