A Novel Network Architecture Support for Fast Reconfiguration

The aim of this paper is to present a novel reconfigurable architecture support which provides efficient access to noncontiguous locations in an array-like structure, whether it be memories or configurable logic blocks (Claw) in reconfigurable systems. This distribution tree (distTree) architecture serves as a mean of address resolution so that no addressing information is required externally or explicitly. It not only reduces the amount of information transferred but also reduces the time for address resolution significantly. A software and a hardware simulators were developed to test the correctness, performance, and hardware resources required for distTree. We found from our simulators that the run-time overhead for address resolution is close to none in most cases while occupying a reasonable amount of hardware area.