High speed algorithm and VLSI architecture design for decoding BCH product codes

In this paper, a sub-optimal algorithm for decoding BCH (t ≥ 2) turbo codes is presented. High speed VLSI decoder architecture is proposed for codes constructed over extended GF(2⁵). While the algorithm applies to higher order BCH product codes, it is shown that this particular block turbo codes, when decoded using the proposed algorithm, gives the best performance (achieving 10⁻⁶ bit error rate at a signal to noise ratio of 2.4 dB) among all two dimensional turbo product codes. Following an analysis of the impact of finite word-length effect on the performance of the SISO decoder, full parallel decoding architecture at the top level and a number of lower level high speed implementation strategies such as applying lookahead technique to reduce the critical path of the merge sort circuit and fast finite field operations are presented. Area and timing estimates obtained by logic synthesis (0.18 µm, 1.5V CMOS technology) from VHDL descriptions are given to show how the design strategies translate into the area consumption and decoding throughput (> 32M bits/s) of the VLSI implementation.