DocumentCode
2877004
Title
A numerical method for efficient failure modelling of three-dimensional bond pad structures
Author
van der Sluis, O. ; van Silfhout, R.B.R. ; Engelen, R.A.B. ; van Driel, W.D. ; Zhang, G.Q. ; Ernst, L.J.
Author_Institution
Philips Appl. Technol., Eindhoven
fYear
2007
fDate
May 29 2007-June 1 2007
Firstpage
235
Lastpage
241
Abstract
Thermo-mechanical reliability issues are major bottlenecks in the development of future microelectronic components. This is caused by the following technology and business trends: (1) increasing miniaturization, (2) introduction of new materials, (3) shorter time-to-market, (4) increasing design complexity and decreasing design margins, (5) shortened development and qualification times, (5) gap between technology and fundamental knowledge development [1]. It is now well established that for future CMOS-technologies (CMOS065 and beyond), low-k dielectric materials will be integrated in the back-end structures [2]. However, bad thermal and mechanical integrity as well as weak interfacial adhesion result in major thermo-mechanical reliability issues. Especially the forces resulting from packaging related processes such as dicing, wire bonding, bumping and molding are critical and can easily induce cracking, delamination and chipping of the IC back-end structure when no appropriate development is performed [3]. The scope of this paper is on the development of numerical models that are able to predict the failure sensitivity of complex three-dimensional microelectronic components while taking into account the details at the local scale (i.e., the back-end structure) by means of a multi-scale method. The damage sensitivity is calculated by means of an enhanced version of the previously introduced area release energy (ARE) criterion. This enhancement results in an efficient and accurate prediction of the energy release rate (ERR) at a selected bimaterial interface in any location. Moreover, due to the two-scale approach, local details of the structure are readily taken into account. In order to evaluate the efficiency and accuracy of the proposed method, several two-dimensional and three-dimensional benchmarks will be simulated. Finally, the failure sensitivity of a three-dimensional back-end structure during a wire pull test is evaluated.
Keywords
CMOS integrated circuits; adhesion; failure analysis; integrated circuit bonding; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; interface phenomena; thermomechanical treatment; CMOS-technologies; IC back-end structures; area release energy criterion; bimaterial interface; damage sensitivity; energy release rate; failure modelling; interfacial adhesion; low-k dielectric materials; mechanical integrity; microelectronic components; multiscale method; thermal integrity; thermo-mechanical reliability; three-dimensional bond pad structures; wire pull test; Adhesives; Bonding; CMOS technology; Dielectric materials; Integrated circuit packaging; Microelectronics; Qualifications; Thermomechanical processes; Time to market; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th
Conference_Location
Reno, NV
ISSN
0569-5503
Print_ISBN
1-4244-0985-3
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2007.373803
Filename
4249889
Link To Document