Universal on-chip communication channel

On-chip communication in mixed-clock systems has become a major issue; especially when asynchronous as well as multiple-clock-domain cores are used in a single chip. This paper proposes a new on-chip communication channel which can be used as asynchronous ⇒ synchronous, synchronous ⇒ asynchronous or synchronous ⇒ synchronous (mixed-clock) communication channel, all with the same design. The synchronization issue, i.e. the metastability, is analyzed; we show that its probability of occurring is practically zero in our designed channel. Because the routers in Asynchronous Network on Chips (ANoCs) are asynchronous and they have to communicate with synchronous cores, the proposed channel is well suited in such systems. Also, other mixed-clock SoCs can equally implement this channel as the interconnection between synchronous IP cores. The proposed channel is simulated in 90 nm CMOS process using Predictive Technology Model (PTM) library with accurate Spice models. The throughput, latency and power consumption of our work are analyzed and compared with existing designs.