DocumentCode
2877056
Title
A 5V-only E2 PROM using 1.5 µ lithography
Author
Dham, V. ; Oto, D. ; Gudger, K. ; Congwer, G. ; Yaw Hu ; Olund, J. ; Nieh, S.
Author_Institution
Intel Corp., Santa Clara, CA, USA
Volume
XXVI
fYear
1983
fDate
23-25 Feb. 1983
Firstpage
166
Lastpage
167
Abstract
A floating-gate E2PROM technology with 1.5μm design rules used to build a 5V-only 2K×8 E2PROM with a cell size of 270μm2and chip area of 23,000 mil2will be described. Typical memory access is 200ns with 450mW power dissipation.
Keywords
Charge pumps; Driver circuits; Feedback circuits; Feedback loop; Isolation technology; Packaging; Power dissipation; Switched capacitor networks; Temperature; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1983.1156502
Filename
1156502
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