Title :
A 64Kb full CMOS RAM with divided word line structure
Author :
Yoshimoto, Masahiko ; Anami, K. ; Shinohara, Hirofumi ; Yoshihara, Tatsuhiko ; Takagi, Hiroyuki ; Nagao, Shijo ; Kayano, S. ; Nakano, T.
Author_Institution :
Mitsubishi LSI Research and Development Laboratory, Itami, Japan
Abstract :
An 8K×8b N-well CMOS static RAM with a divided word line architecture which decreases both the column current and word line delay will be described. The RAM achieves an access time of 50ns while dissipating 100mW. The use of molybdenum silicide as a substitute for the second polysilicon layer will be reviewed.
Keywords :
CMOS process; CMOS technology; Capacitance; Circuits; Clocks; Decoding; Delay; Large scale integration; Random access memory; Read-write memory;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1983.1156503
