DocumentCode :
2877077
Title :
3D Multi Scale Modeling of Wire Bonding Induced Peeling in Cu/Low-k Interconnects: Application of an Energy Based Criteria and Correlations with Experiments
Author :
Fiori, Vincent ; Beng, Lau Teck ; Downey, Susan ; Gallois-Garreignot, Sebastien ; Orain, Stephane
Author_Institution :
STMicroelectron., Crolles
fYear :
2007
fDate :
May 29 2007-June 1 2007
Firstpage :
256
Lastpage :
263
Abstract :
This paper aims to demonstrate the compliance of the proposed modeling approach with the aids of experimental validations. 3D multi scale simulation of both bonding process and wire pull test is carried out. Using a previously validated homogenization procedure to include pad structure description even at the global scale, stress fields acting in the copper/low-k stack are evaluated. The modeling strategy also includes an in-house developed energy based analysis. For the experimental part, a wide range of wire bond trials have been performed in order to qualify the 65-nm technology node. On behalf of that, several bond pad architectures have been implemented and wire bonded on a test vehicle. It was found a significant effect of the copper/low-k design on peeling failure rates, in particular with severe bonding conditions. In this paper, typical modeling results are presented. Contrary to stress based one, the energy based analysis shows a better ability to forecast the observed failed interface. From simulation results obtained, it is confirmed that the bonding process plays major role in the peeling failure, despite the fact that most of them are observed during the wire pull test. Failure mechanisms are also proposed. Then, the implemented pad structures are evaluated and analyzed. Both general trends and architecture ranking are provided. Simulations are then faced to experimental results and a full agreement is found. The complementary nature of the energy based failure criteria is again highlighted through a clearer discrimination of the tested structures. Finally, the simulation procedure with confirmed experimental results demonstrates its ability in design and process optimizations by providing a better understanding of pad peeling failure mechanisms.
Keywords :
adhesion; copper; failure analysis; integrated circuit interconnections; integrated circuit modelling; lead bonding; low-k dielectric thin films; 3D multi scale modeling; Cu; IC chips; bond pad architectures; copper interconnects; design optimization; energy based analysis; homogenization procedure; low-k dielectric material interconnects; pad peeling failure mechanisms; pad structure description; process optimization; size 65 nm; thermosonic wire bonding process; wire bonding induced peeling; wire pull test; Bonding processes; Copper; Design optimization; Failure analysis; Load forecasting; Process design; Stress; Testing; Vehicles; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th
Conference_Location :
Reno, NV
ISSN :
0569-5503
Print_ISBN :
1-4244-0985-3
Electronic_ISBN :
0569-5503
Type :
conf
DOI :
10.1109/ECTC.2007.373806
Filename :
4249892
Link To Document :
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