DocumentCode :
2877107
Title :
A circuit design methodology for CMOS microcomputer LSIs
Author :
Nakamura, Hajime ; Kita, Yoshihiro ; Funabashi, Toshihisa ; Maejima ; Kihara, Takashi
Author_Institution :
Hitachi Central Research Laboratory, Tokyo, Japan
Volume :
XXVI
fYear :
1983
fDate :
23-25 Feb. 1983
Firstpage :
134
Lastpage :
135
Abstract :
A structured approach to CMOS circuit block coupling and a simplified circuit delay evaluation method will be presented. Cited will be results for an 8b 30mW CMOS microcomputer with 80,000 transistors.
Keywords :
CMOS technology; Circuit synthesis; Clocks; Energy consumption; Frequency estimation; Kernel; Microcomputers; Propagation delay; Read only memory; Satellites;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
Type :
conf
DOI :
10.1109/ISSCC.1983.1156506
Filename :
1156506
Link To Document :
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