DocumentCode
2877139
Title
Building block approach and variable size memory for CMOS VLSIs
Author
Koide, K. ; Ohba, Tsuyoshi ; Ikuzaki ; Fujita, Masayuki ; Masaki, A. ; Kato, Masaaki ; Murata, Shotaro
Author_Institution
Hitachi Device Development Center, Tokyo, Japan
Volume
XXVI
fYear
1983
fDate
23-25 Feb. 1983
Firstpage
148
Lastpage
149
Abstract
This report will discuss 10K to 20K CMOS VLSIs with a building block approach suitable for high speed and automated design. To accommodate diversified designers´ demands, RAMs and ROMs have been designed to be size variable and applicable to the DA system. Three hierarchical levels are cell, block and chip. Two layer metals (aluminum) and one layer (poly-Si) were used for wiring.
Keywords
Circuits; Delay; Design automation; Random access memory; Read only memory; Read-write memory; Routing; System testing; Very large scale integration; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1983.1156509
Filename
1156509
Link To Document