Single low-supply and low-distortion CMOS analog multiplier

Author

Prommee, Pipat ; Somdunyakanok, Montri ; Angkaew, Krit ; Jodtang, Arkhom ; Dejhan, Kobchai

Author_Institution

Fac. of Eng., King Mongkut´´s Inst. of Technol. Ladkrabang, Bangkok, Thailand

Volume

1

fYear

2005

fDate

12-14 Oct. 2005

Firstpage

251

Lastpage

254

Abstract

A single low-supply CMOS analog multiplier based upon ohmic region of MOS transistors is presented. This paper describes a method to force the drain-source voltage (V_DS) of MOS transistors to operate in ohmic region. The achieved circuit can be used a single low-power supply. The complete circuit contains 20 transistors and 8 current sources using a low-power supply +1.5 volts. This circuit has high performance with very high-linearity and low-distortion. The achieved input dynamic range operation is ±400 mV, the linearity error is smaller than 0.1% and total harmonic distortion is smaller than 0.25% for input range 800 mVp-p.

Keywords

CMOS analogue integrated circuits; MOSFET; analogue multipliers; low-power electronics; 1.5 V; CMOS analog multiplier; MOS transistors; drain-source voltage; total harmonic distortion; CMOS technology; Circuits; Current supplies; Dynamic range; Information technology; Linearity; MOSFETs; Transconductance; Virtual colonoscopy; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technology, 2005. ISCIT 2005. IEEE International Symposium on

Print_ISBN

0-7803-9538-7

Type

conf

DOI

10.1109/ISCIT.2005.1566843

Filename

1566843