DocumentCode
2877269
Title
Design of Extreme Connector Stacking in PCI Express Interface
Author
Herrman, B. ; Patel, P. ; Mutnury, B. ; Cases, M. ; Pham, N. ; de Araujo, D.N.
Author_Institution
IBM Syst. & Technol. Group, Research Triangle Park
fYear
2007
fDate
May 29 2007-June 1 2007
Firstpage
339
Lastpage
345
Abstract
This paper describes the electrical architecture and design of the PCI express interface in the Blade Centertrade (J.E. Hughes et al., 2000) system. A comprehensive electrical design methodology, including accurate and detailed modeling and simulation of the complete design space, is required in order to achieve the speeds required by this interface, while using low-cost printed circuit board materials. In this paper, some of the obstacles and solutions to support 2.5 Gb/s to 5 Gb/s data transmission over multiple boards and multiple connector technologies are highlighted. Pre-layout analysis was performed to predict the interconnect performance for relatively long trace lengths in FR-4 material across four connectors in order to satisfy the PCI express design requirements and guarantee the overall performance objective of the system. Signal integrity affects (including frequency dependent losses, inter-symbol-interference (ISI), crosstalk, impedance discontinuities, via and pad capacitance effects and skew) were integrally analyzed across the complete design space. The solution provided was stack connector arrangements integrated into the PCI express link. The benefit was greater density, but a product that could be customized. This paper concludes the correlation between a post route simulation result and lab measurements. The correlation of simulation results with hardware measurements provided a high confidence in the simulation methodology, which could be relied upon in developing the broader set of PCB based design guidelines.
Keywords
electric connectors; printed circuit layout; BladeCenter; FR-4 material; ISI; PCI express interface; crosstalk; data transmission; electrical design methodology; extreme connector stacking; frequency dependent losses; impedance discontinuities; interconnect performance; intersymbol-interference; pad capacitance effects; pre-layout analysis; signal integrity affects; Blades; Circuit simulation; Connectors; Data communication; Design methodology; Integrated circuit interconnections; Performance analysis; Printed circuits; Space technology; Stacking;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th
Conference_Location
Reno, NV
ISSN
0569-5503
Print_ISBN
1-4244-0985-3
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2007.373820
Filename
4249906
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