Design space exploration for DSP applications using the ASIP development system PEAS-III

This paper describes rapid design space exploration for DSP applications using the PEAS-III system, which is a configurable processor development environment for application domain specific embedded systems. First, a compiler generation method, which is one of the key technologies in the PEAS-III system, is proposed. The target compiler is generated from the same information as used for the synthesizable HDL generation of the target processor. Using the PEAS-III system, not only the processor HDL description but also its target compiler are generated. Therefore, execution time which is computed from execution cycles of applications and generated processor´s frequency can be rapidly evaluated. Experimental results showed that the trade-offs between area and performance of processors for DCT and FIR filter applications were analyzed in 4.1 hours and the optimal processor was selected under the design constraint by using generated compilers and processors.