Electrical Performance of an Organic, Z-interconnect, Flip-Chip Substrate

We have designed test vehicle (TV) using the Z-interconnect building blocks, to make new RF structures. Specifically, large rectangular clearances were cut in multiple ground planes to make a very wide 50-ohm stripline. Also, typical 50-ohm stripline was designed with a ground-signal-ground structure. Each stack-up had 16 metal layers, including 3 0S2P joining cores, 2 2S2P signals cores, plated copper on top and bottom and embedded resistance on layer 7. Two different material sets were used. One was a mixed set of materials, using different materials or the plane-dielectric-plane structure and for the dielectric layers associated with the signal layers. Dielectric 1 has Dk = 3 and tanzeta= .003. Dielectric 2 has Dk = 3.2 and tanzeta = .003. Resistance change for embedded resistors for different materials set is not significant. Conducting adhesives formulated using silver and Low melting point (LMP) fillers were used to fill small diameter holes for Z-interconnect applications. Laminated conducting joints show low resistance in the range of 10-12 milliohm per square inch. Detailed electrical performances of the TV are under investigations. Electrical performance tests include S-parameter measurements of stripline structures. Very low signal loss to 25GHz will be shown. Evaluation criteria for the test vehicle will include its ability to perform as a reliable, manufacturable, high-performance substrate.