DRAM failure cases under hot-carrier injection

In IIRW 2010, we presented new reliability stress methods (a.k.a. one ROW fast access) for dynamic random access memory (DRAM) hot-carrier injection (HCI) robustness qualifications. In IRPS 2011, we presented the systematic simulation methodology for DRAM HCI robustness. This is the follow-up paper for our two previous papers. We wrote our two previous papers because we experienced DRAM field failures due to HCI weakness. Due to the nature of the HCI failure mechanisms, physical failures were not visually inspected and visual based approach was not effective. This paper will provide different DRAM failure modes, all attributed to HCI as a root cause. Since we have to use the electrical failure analysis method, we believe it is important to document the method, the affected circuit, and the system signatures for the industrial community.