DocumentCode :
2877341
Title :
A 100ns 256K DRAM with page-nibble mode
Author :
Shimotori, K. ; Fujishima, Kenzaburo ; Ozaki, Hiroaki ; Uoya, S. ; Nagatomo, Makoto ; Saitoh, Kunimasa ; Oka, Hikaru
Author_Institution :
Mitsubishi LSI Research and Development Laboratory, Itami, Japan
Volume :
XXVI
fYear :
1983
fDate :
23-25 Feb. 1983
Firstpage :
228
Lastpage :
229
Abstract :
This paper will report on a 256K×1b 100ns access time DRAM which functions in both page and nibble mode, distinguished internally by the 
precharge time. The device is immune to voltage bumping and uses laser programmable redundancy.
precharge time. The device is immune to voltage bumping and uses laser programmable redundancy.Keywords :
Buffer storage; Content addressable storage; Decoding; Delay effects; Large scale integration; Random access memory; Read-write memory; Redundancy; Variable structure systems; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
Type :
conf
DOI :
10.1109/ISSCC.1983.1156520
Filename :
1156520
Link To Document :
