DocumentCode :
2877348
Title :
A 34ns 256Kb DRAM
Author :
Natori, K. ; Furuyama, Toshiya ; Saito, Sakuyoshi ; Fujii, Shohei ; Toda, Hiroaki ; Tanaka, T. ; Ozawa, O.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Volume :
XXVI
fYear :
1983
fDate :
23-25 Feb. 1983
Firstpage :
232
Lastpage :
233
Abstract :
A 256K × 1b MOS DRAM, using power circuits and MoSi2 gate transistors, will be reported. Division of the chip into eight blocks results in 34ns 
access time, 94ns 
and 170mW active power.
access time, 94ns and 170mW active power.Keywords :
Capacitors; Content addressable storage; Decoding; Electronics packaging; Emergency power supplies; MOSFETs; Random access memory; Testing; Timing; Variable structure systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
Type :
conf
DOI :
10.1109/ISSCC.1983.1156521
Filename :
1156521
Link To Document :
