Performance Modeling for Carbon Nanotube Interconnects in On-Chip Power Distribution

A novel paradigm is proposed to potentially use thin single-wall carbon nanotube (SWNT) signal interconnects and large-diameter multi-wall carbon nanotube (MWNT) power interconnects in the second interconnect level. Using physical circuit models for SWNTs and MWNTs, it is demonstrated that by the end of the ITRS the proposed approach can improve the sheet resistance of power interconnects by up to 3 times, improve the speed of local signal interconnects by 50%, and lower their dynamic power dissipation by more than two times. In the first interconnect level, a hybrid system of power copper wires and thin SWNT signal interconnects would offer the same improvements for signal interconnects and allow utilizing thick copper wires with no performance or power penalties for signal interconnects. At the global levels, it is shown a minimum density of 1 metallic SWNT per 2.5 nm² cross-sectional area is needed to outperform copper power interconnects. Power grids made out of MWNTs can offer smaller resistances compared to copper grids only if very coarse grids with grid pitches larger than 20 mum are needed.