DocumentCode
2877604
Title
A sensitivity analysis of a new hardware-supported Global Synchronization Unit
Author
Lynch, Elizabeth Whitaker ; Riley, George F.
Author_Institution
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA
fYear
2009
fDate
21-23 Sept. 2009
Firstpage
1
Lastpage
4
Abstract
Historically, large-scale low-lookahead parallel simulation has been a difficult problem. As a solution, we have designed a global synchronization unit (GSU) that would reside centrally on a multi-core chip and asynchronously compute the lower bound on time stamps (LBTS), the minimum timestamp of all unprocessed events in the simulation, on demand to synchronize conservative parallel simulators. Our GSU also accounts for transient messages, messages that have been sent but not yet processed by their recipient, eliminating the need for the simulator to acknowledge received messages. In this paper we analyze the sensitivity of simulation performance to the time required to access the GSU. The sensitivity analysis revealed that with GSU access times as high as hundreds of cycles, there was still a significant performance advantage over the baseline shared-memory implementation.
Keywords
microprocessor chips; sensitivity analysis; synchronisation; baseline shared-memory implementation; hardware-supported global synchronization unit; large-scale low-lookahead parallel simulation; lower bound on time stamps; multicore chip; multicore systems; sensitivity analysis; Acceleration; Analytical models; Computational modeling; Computer simulation; Concurrent computing; Discrete event simulation; Error correction; Hardware; Scalability; Sensitivity analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Modeling, Analysis & Simulation of Computer and Telecommunication Systems, 2009. MASCOTS '09. IEEE International Symposium on
Conference_Location
London
ISSN
1526-7539
Print_ISBN
978-1-4244-4927-9
Electronic_ISBN
1526-7539
Type
conf
DOI
10.1109/MASCOT.2009.5367047
Filename
5367047
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