DocumentCode
2877665
Title
ON THE TESTABLE DESIGN OF BILATERAL BIT-LEVEL SYSTOLIC ARRAYS
Author
Bandyopadhyay, Subir ; Bhattacharya, Bhargab B.
fYear
1991
fDate
26-30 Oct 1991
Firstpage
1024
Keywords
Automatic testing; Computer science; Hardware; Logic arrays; Logic testing; Parallel algorithms; Performance evaluation; Signal processing; Systolic arrays; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1991, Proceedings., International
ISSN
1089-3539
Print_ISBN
0-8186-9156-5
Type
conf
DOI
10.1109/TEST.1991.519770
Filename
519770
Link To Document