Title :
A Computer Architecture for High Pin Count Testers
Author :
Hannaford, Christopher J.
Keywords :
Computer architecture; Concurrent computing; Error correction codes; Hardware; Instruments; Logic devices; Logic testing; Signal design; Timing; Voltage;
Conference_Titel :
Test Conference, 1991, Proceedings., International
Print_ISBN :
0-8186-9156-5
DOI :
10.1109/TEST.1991.519772
