Title :
Submicron VLSI memory circuits
Author :
Mano, Toru ; Yamada, J. ; Inoue, Junichi ; Nakajima, Shigeru
Author_Institution :
NTT Musashino Electrical Communication Laboratory, Tokyo, Japan
Keywords :
Circuit testing; Clocks; Decoding; Error correction; Error correction codes; MOS devices; Random access memory; Read-write memory; Threshold voltage; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1983.1156549
