• DocumentCode
    2877872
  • Title

    Submicron VLSI memory circuits

  • Author

    Mano, Toru ; Yamada, J. ; Inoue, Junichi ; Nakajima, Shigeru

  • Author_Institution
    NTT Musashino Electrical Communication Laboratory, Tokyo, Japan
  • Volume
    XXVI
  • fYear
    1983
  • fDate
    23-25 Feb. 1983
  • Firstpage
    234
  • Lastpage
    235
  • Keywords
    Circuit testing; Clocks; Decoding; Error correction; Error correction codes; MOS devices; Random access memory; Read-write memory; Threshold voltage; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1983.1156549
  • Filename
    1156549
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2877872