Full Device Exposure Laser Thermal Annealing: High performance and high yield junction formation process

Pulsed Laser Thermal Annealing (LTA) of Silicon in the nanosecond regime has attracted a considerable attention regarding the activation process for nanodevices. Pulsed LTA with an Excimer laser is of a particular interest for the activation of dopants in shallow implanted layers such as the backside junction formation for 3D-integrated devices including sensing devices. Indeed, high activation of the surface layer can be achieved in the melt regime, without harming the underlying buried device layers. In this work, junction formation with LTA on thick SOI is studied. Shallow junctions below 100nm with 85% activation rate were obtained. Moreover, it was hinted that a uniform and stitchless annealing process is necessary to achieve high sensor performance. Here, the ability of the Full Device Exposure (FDE) feature of the LTA tool to adapt the processed area to various sensor geometries is demonstrated. Finally, the influence of overlap is characterized on actual devices, showing peaked non uniformity of the sensor response in the overlap region, thus confirming the need for the FDE feature.