Title :
Optimization of Cu electrodeposition parameters for Through Silicon Via (TSV)
Author :
Noh, Sang-Soo ; Choi, Eun-Hey ; Lee, Yong-Hyuk ; Ju, Hyun-jin ; Rha, Sa-Kyun ; Lee, Boung-ju ; Kim, Dong-Kyu ; Lee, Youn-Seoung
Author_Institution :
Dept. of Inf. & Commun. Eng., Hanbat Nat. Univ., Daejeon, South Korea
Abstract :
We investigated an optimal condition for void-free Cu filling in trench and TSV according to variation of plating DC current density. The copper deposit growth mode in and around the trench (width 100 μm and AR 1) was measured. The deposition rate of top layer on trench was similar to the measured Cu deposition rate on the plane wafer. However, the deposition rate in Cu electroplating was different from the top of the trench and the bottom of it according to variation of plating current density. We found that the deposition rate for all positions (top, bottom, and side-wall) was more uniform at lower plating current density. By application of this growth mode in trench, we could fill copper without void in TSVs of size from diameter 20 μm (AR 4) to 10 μm (AR 6) by Cu electroplating.
Keywords :
copper; current density; electroplating; optimisation; three-dimensional integrated circuits; Cu; Cu electrodeposition parameters; Cu electroplating; DC current density; TSV; copper deposit growth mode; optimization; plating current density; through silicon via; void-free Cu filling; Copper; Current density; Filling; Films; Silicon; Three dimensional displays; Through-silicon vias;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2011 18th IEEE International Symposium on the
Conference_Location :
Incheon
Print_ISBN :
978-1-4577-0159-7
Electronic_ISBN :
1946-1542
DOI :
10.1109/IPFA.2011.5992776