A 5-μm-width multi-layer wafer-level Cu wiring technology with resin CMP for highly-reliable FCBGA

A three-layer wafer-level copper wiring technology adaptable to a large flip-chip ball-grid array (FCBGA) package is successfully developed. This technology features fine 10-mum-pitch copper wiring, with 5-mum thickness, fabricated by a semi-additive process that employs a resin CMP process making each layer flat. A non-photosensitive polyimide is adopted as an insulating material, because it has superior mechanical properties compared to epoxy resin. A prototype chip with a size of 17.3times17.3-mm and three-layer copper wiring is fabricated and packaged into a 50times50-mm FCBGA. This prototype package demonstrates excellent long-term reliability in high-temperature and humidity bias tests (HHBT) and chip-level and package-level thermal-cycle tests (TCTs). Our technology is suitable for future low-cost ULSI wiring and long-distance data-transmission lines in a system-in-package (SiP).