Parallel programming on the Convex MPP

The future evolution of high performance computing hardware will be largely pointed towards massively parallel processors (MPP). There is a general agreement in the industry that these MPPs will be constructed from commodity RISC processors and that they will be in the MIMD class. The larger, and still open, issues are centered on the transition from our current software, algorithms, and programming states to those that are appropriate for MPPs. This transition has, to date, been demonstrated as being non-trivial. There exist certain technologically achievable things in MPP hardware and software that will aid in making the transition, not necessarily trivial but certainly, easier. This paper looks at the interaction of MPP hardware with programming and algorithm selection. Our particular vehicle is the Convex MPP