Title :
Low-Temperature High-Density Chip-Stack Interconnection Using Compliant Bump
Author :
Watanabe, Naoya ; Asano, Tanemasa
Author_Institution :
Kumamoto Technol. & Ind. Foundation, Kumamoto
fDate :
May 29 2007-June 1 2007
Abstract :
We demonstrate low-temperature high-density chip-stack interconnection using compliant bump. Low temperature chip stacking was carried out by two methods; (1) plasma cleaning of compliant bumps, (2) mechanical caulking using compliant bump and doughnut-shaped electrode. The latter method is very effective in realizing chip stacking even at room temperature.
Keywords :
integrated circuit interconnections; low-temperature high-density chip-stack interconnection; mechanical caulking; plasma cleaning; three-dimensional chip-stacking technology; Bonding; Capacitive sensors; Cleaning; Gold; Integrated circuit interconnections; Plasma temperature; Resins; Resists; Sensor arrays; Stacking;
Conference_Titel :
Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th
Conference_Location :
Reno, NV
Print_ISBN :
1-4244-0985-3
Electronic_ISBN :
0569-5503
DOI :
10.1109/ECTC.2007.373861
