Title :
A 20ns CMOS functionable gate array with a configurable memory
Author :
Sano, Tomomi ; Matsukuma, S. ; Hashimoto, Koji ; Ohuchi, Y. ; Kudo, O. ; Yamamoto, Hiroshi
Author_Institution :
Nippon Electric Co., Ltd., Kanagawa, Japan
Abstract :
A CMOS gate array with 4,368 gates and 2,304 bits of configurable memory, using 1.5μm design rules, will be discussed. The memory can change word × bit configuration as well as to increase the gate array function.
Keywords :
Artificial intelligence; Bonding; Chip scale packaging; Delay; Inverters; Metallization; National electric code; Pins; Variable structure systems; Wiring;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1983.1156558
