Reaction Engineering of Through-Chip Via Filling for Wafer-Level 3D Packaging

Through-chip vias, 170 microns in depth and 10 to 35 microns in diameter were filled by electrodeposition of copper. The process was optimized for reliability and speed through a combination of process modeling, electro-analytical studies and pilot scale plating on 8-inch wafers in a commercial process unit. The approach is based on use of reverse pulses and oxygen diffusers to maintain an optimum distribution of accelerator over the wafer. Results of electroanalytical studies on a rotating disk electrode (RDE) and rotating ring-disk electrode (RRDE) are presented to demonstrate quantitatively the role of transport-limited redox processes in regulating the distribution of accelerant within vias. Results of dimensional analysis and numerical simulation are presented and used to relate the electroanalytical results with the proposed mechanism. A three-hour pilot-scale plating process optimized through application of these results is demonstrated for 170 micron deep vias.