DocumentCode :
2878110
Title :
Stress induced hump in p-channel poly-Si TFTs under dynamic negative bias temperature stress
Author :
Zhou, Jie ; Wang, Mingxiang ; Wong, Man
Author_Institution :
Dept. of Microelectron., Soochow Univ., Suzhou, China
fYear :
2011
fDate :
4-7 July 2011
Firstpage :
1
Lastpage :
4
Abstract :
The dynamic negative bias temperature (NBT) stress induced hump phenomenon in p-channel poly-Si TFTs has been investigated. The hump only shows up after the stress. It is found to appear along with the positive shift of device Vth and disappears after a certain stress time. The hump phenomenon is closely related to the dynamic effect, and shows the same dependency on the pulse amplitude and stress temperature with the dynamic effect. The presence of parasitic edge transistor at the channel width side is thought to be responsible for the hump phenomenon.
Keywords :
elemental semiconductors; silicon; thin film transistors; Si; device positive shift; dynamic negative bias temperature stress; p-channel poly-Si TFT; parasitic edge transistor; pulse amplitude; stress induced hump; stress temperature; Degradation; Electric fields; Impact ionization; Logic gates; Stress; Thin film transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2011 18th IEEE International Symposium on the
Conference_Location :
Incheon
ISSN :
1946-1542
Print_ISBN :
978-1-4577-0159-7
Electronic_ISBN :
1946-1542
Type :
conf
DOI :
10.1109/IPFA.2011.5992787
Filename :
5992787
Link To Document :
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