Dependability assessment of the time-triggered SoC prototype using FPGA fault injection

The high integration of current silicon devices leads to growing transient failure rates for multi-core based embedded systems. As a consequence, we can develop on-chip fault tolerance solutions to increase the reliability of Multi-Processor Systems-on-a-Chip (MPSoCs), for instance, the active redundancy of cores (e.g., on-chip Triple Modular Redundancy) which requires independence among the replicated cores to avoid common mode failures. For this purpose, fault containment mechanisms have been developed as part of a Time-Triggered System-on-Chip (TTSoC) architecture. This paper experimentally evaluates the TTSoC architecture which comprises a time-triggered Network-on-a-Chip (NoC) and network interfaces serving as guardians. We quantify the reliability of a TTSoC prototype using FPGA emulated transient fault injection. We assess the fault containment and the reliability increase by on-chip TMR in the TTSoC. Finally, we identify the most sensitive areas of the architecture in the network interfaces of the cores.