Title :
1.5 µm scaled CMOS microcomputer technology
Author :
Liu, Siyuan ; Atwood, Greg ; So, Eddy ; Wu, Bin ; Leftwich, R. ; Hasserjian, K.
Author_Institution :
Intel Corporation, Santa Clara, CA, USA
Abstract :
This paper will discuss the application of 1.5μm CMOS technology by integrating existing NMOS devices with an N-well CMOS approach. Bulk P- substrates were replaced with Pepi on P+ substrates for reduced latchup susceptability. Minimum gate delays of 190ps and a 36% linear shrinkage of an 8b microcomputer have been realized.
Keywords :
CMOS technology; Delay; Dielectrics; Geometry; Microcomputers; Paper technology;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156571
