DocumentCode
2878285
Title
1.5 µm scaled CMOS microcomputer technology
Author
Liu, Siyuan ; Atwood, Greg ; So, Eddy ; Wu, Bin ; Leftwich, R. ; Hasserjian, K.
Author_Institution
Intel Corporation, Santa Clara, CA, USA
Volume
XXVII
fYear
1984
fDate
22-24 Feb. 1984
Firstpage
156
Lastpage
157
Abstract
This paper will discuss the application of 1.5μm CMOS technology by integrating existing NMOS devices with an N-well CMOS approach. Bulk P- substrates were replaced with Pepi on P+ substrates for reduced latchup susceptability. Minimum gate delays of 190ps and a 36% linear shrinkage of an 8b microcomputer have been realized.
Keywords
CMOS technology; Delay; Dielectrics; Geometry; Microcomputers; Paper technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location
San Francisco, CA, USA
Type
conf
DOI
10.1109/ISSCC.1984.1156571
Filename
1156571
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