Effects of Organic Package Warpage on Microprocessor Thermal Performance

Efficient heat dissipation is a major challenge for the packaging of high power microprocessors. This paper discusses a novel lid assembly process and characterization techniques that were successfully developed for a high power microprocessor in high volume production. For a high power microprocessor flip chip organic package with under fill, die warpage as a result of CTE mismatch between the silicon and organic substrate is a challenge. A laser-based surface profiling technique was used to characterize the die and package warpage. Die warpage is a function of temperature. There is little die warpage at under fill curing temperatures (stress-free stage), but die warpage increases when the package is cooled from under fill curing temperature to room temperature. The bond line thickness of the thermal interface material between the die and the lid (TIM1) is critical for microprocessor thermal performance, and there is significant TIM bond line thickness variation from die edge/corner to die center as a result of the die warpage. TIM is in compression at the die center and in tension at die edges and die corners. Parallelism between the silicon die and lid surface is another critical factor. If there is serious lid tilt with respect to silicon die surface, one side of TIM will be stretched more that the other side after cooling. Therefore, lid tilt is another factor requires good process control. C-mode scanning acoustic micrography (CSAM) was found to be effective in revealing TIM faults when certain polymers TIMs are used. Another challenge in characterizing the TIM bond line thickness (BLT) is the nature of the gel-type TIM. Even though it is cured, the TIM remains very soft and compliant, which is the desirable property for a good thermal performance and reliability.