Title :
3D LSI and reliability
Author :
Koyanagi, Mitsumasa
Author_Institution :
New Ind. Creation Hatchery Center, Tohoku Univ., Sendai, Japan
Abstract :
Three-dimensional (3D) integration technologies including a new 3D heterogeneous integration of super-chip are described. In addition, reliability issues in these 3D LSIs such as mechanical stresses induced by through-silicon vias (TSVs) and metal microbumps and Cu contamination in thinned wafers are discussed. Furthermore, design and test methodologies to improve the reliability of 3D LSIs are discussed.
Keywords :
copper; integrated circuit reliability; large scale integration; surface contamination; three-dimensional integrated circuits; 3D LSI; 3D heterogeneous integration; Cu; Cu contamination; TSV; mechanical stresses; metal microbumps; reliability; super-chip; thinned wafers; three-dimensional integration technology; through-silicon vias; Bonding; Copper; Silicon; Stress; Substrates; Three dimensional displays;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2011 18th IEEE International Symposium on the
Conference_Location :
Incheon
Print_ISBN :
978-1-4577-0159-7
Electronic_ISBN :
1946-1542
DOI :
10.1109/IPFA.2011.5992802
