Wafer scale integration

With lowering defect densities in LSI fabrication technologies interest in wafer scale integration has revived. The process holds the promise of higher performance, lower cost, and increased packing density, particularly at the system level. However, it is necessary to consider if recent advances are sufficient to outweigh problems in testing, repairability and system configuration, ancl flexibility. To be assessed too are the problems that limited early implementations in the 60s and if they can be overcome; and if wafer scale integration will provide new opportunities such as systolic arrays, connection-oriented architectures and other related disciplines . . . Panelists will discuss unique technological approaches and the future potentials along with limitations that may arise.